1. Field of the invention
The present invention relates to an address generating circuit for generating an address to detect or correct data errors.
2. Description of the prior art
In, for example, a CD-ROM system or CD-I system, parity symbols (redundant data) named P parity and Q parity are added to digital data to correct data errors. By constructing error correcting codes composed of distributed data, it is possible to distribute errors which tend to be uneven so as to effectively give play an ability for error correction. Decoding P and Q codes composed of such data and parity symbols requires generating addresses in a complex manner.
One approach for such an address generation is to generate the address as software by utilizing a microcomputer. However, this creates a problem where the processing speed of the microcomputer is slow.
In addition, a table look-up system is known, in which the address necessary for decoding the code which is stored in advance in the memory is stored in a ROM and the address for decoding is obtained by utilizing the ROM. Such a table look-up system has a simple structure and a high processing speed. However, since it requires use of a ROM, it is for example difficult to build in an LSI as a decoding circuit of the CD-ROM system. Furthermore, where the error correcting code is formed by adding a P parity of 86 bytes and a Q parity of 52 bytes to the data of 1032 bytes as shown in pages 73-80 of "Electronics" Dec., 1985, the address of the output data from the ROM for generating the address for decoding the P code and the address of the output data from the ROM for generating the address for decoding the Q code become 11 bits, respectively. This makes it necessary to use at least two ROMs having a standard specification (see FIG. 17).